PCB Board Design: How to Reduce Errors and Improve Efficiency?

Circuit board design is a critical and time-consuming task, and any problem that arises requires the engineer to examine the entire design on a component-by-cell basis, on a component-by-component basis. It can be said that the board factory design requirements are as careful as the chip design.

A typical circuit board design flow consists of the following steps:

The first three steps take the most time because the schematic check is a manual process. Imagine a SoC board factory with 1000 or more connections. Checking each connection manually is a tedious task. In fact, it is almost impossible to inspect each connection, which will cause problems for the final circuit board manufacturer, such as wrong connection and floating nodes.

The schematic capture phase generally faces the following types of problems:

● Underscore error: such as APLLVDD and APLL_VDD

● Case issues: such as VDDE and vdde

● Misspell

● Signal short circuit problem

● Plenty more

To avoid these errors, there should be a way to check the complete schematic in seconds. This method can be implemented with schematic simulation, which is rarely seen in the current circuit board design flow. Schematic simulation allows you to observe the final output at the required node, so it automatically checks all connection issues.

In a complex circuit board design, the number of connections may reach thousands, and a very small amount of change is likely to waste a lot of time checking.

Schematic simulation can not only save design time, but also improve the quality of the circuit board factory, and improve the efficiency of the entire process.

A typical device under test (DUT) has the following signals:

1. Clock Signal : The clock signal is one of the most important signals in a digital circuit and is used to synchronize the operation of various components. In PCB design, the clock signal is often a differential clock signal to improve immunity to interference and transmission stability1.

2. Data Signals: Data signals are used to transmit and process data. In DDR memory, data signals include DQ, DQM, and DQS, which require strict timing control and isometric requirements to ensure accurate data transmission1.

3. Address signal: An address signal is used to specify the location where data is stored or processed. In DDR memory, address signals include ADDR, BA, RAS, CAS, WE, etc.1.

4. Control Signal: The control signal is used to control the operation mode of the memory, such as CS#, CLK, ODT, etc. 1.

The device under test will have a variety of signals after some pre-adjustment, and there are various modules, such as regulators, op amps, etc., for signal conditioning. Consider an example of a power signal derived from a regulator:

• Proportional adjuster

  
  

• Proportional integration regulator

  
  

• Proportional differential regulator

In order to verify the connection relationship and perform an overall check, schematic simulation was used. Schematic simulation consists of schematic creation, test bench creation, and simulation.

In the test platform creation process, there will be a stimulus signal to the necessary input, and then observe the output at the signal point of interest.

This can be done by connecting the probe to the node to be observed. Node voltages and waveforms can indicate whether the schematic has errors. All signal connections are automatically checked.

Let's take a look at a part of the picture above where the probe node and voltage are clearly visible:

Therefore, with the help of simulation, we can directly observe the results and confirm whether the circuit board schematic is correct. In addition, design changes can be investigated by carefully adjusting the stimulus signal or component values. So the schematic simulation can save a lot of time for circuit board design and inspection personnel, and increase the chance of design correctness.