PCB Via Treatments Explained: Tenting vs. Plugging vs. Exposed Vias & How to Specify Them

Written By:Syspcb Updated: 2025-8-13

Vias (plated through-holes) connect PCB layers, but their finishing treatment determines reliability, solderability, and signal integrity. Misunderstanding “Tenting,” “Plugging,” and “Exposed” vias causes 23% of DFM failures. Here’s how to specify them correctly:


TermProcessVisualBest ForAvoid When
TentingSolder mask covers via hole & pad⬤ Green-coveredCost-sensitive designs, signal viasHigh-current/thermal vias
PluggingVia filled with epoxy before mask coat⬤ Flat surfaceBGA escape routes, HDI boardsHigh-frequency RF (>10 GHz)
ExposedSolder mask removed from via pad⬤ Metallic ringThermal vias, test pointsHigh-corrosion environments
PCB Via Treatments Explained

  • Plugged vias block solder migration → Reduce BGA voids by 40%
    • Tented vias risk mask cracks → Solder wicks into hole during reflow
  • Exposed vias: Direct thermal path → 40% lower RθJA vs. tented
    • Plugged vias: Thermal epoxy conducts heat 5× better than air
  • Tenting: Prevents contamination in RF vias → <0.1dB loss @ 6GHz
    • Plugging: Avoids impedance discontinuities in HDI microvias
PCB Via Treatments Explained

Untreated via holes trap chemicals → CAF failure risk ↑300% in humid environment


Clear Instructions Prevent Manufacturing Errors:

// EXAMPLE SPECIFICATION //    
VIA TREATMENT:    
– All vias under 0.3mm: PLUGGED (IPC-4761 Type VII)    
– Thermal vias (PAD_THERM1-4): EXPOSED + Cu-filled    
– Remaining vias: TENTED (solder mask over annular ring)    

IPC Standards Reference:
IPC-4761: Via protection types (Type I-VII)
IPC-6012: Acceptability criteria for plugged vias


Manufacturers issue EQs when via specs are unclear. Respond strategically:

Your Response:
“Apply tenting for vias <0.5mm, plugging for vias under BGAs (components U1-U6), and expose thermal vias (pads marked ‘TH’). Refer to layer 28 drill file for via classifications.”

Your Response:
“Accept tenting with solder mask ink filling (IPC-4761 Type II) for vias <0.2mm. Ensure 100% mask coverage over annular rings.”

Your Response:
“Add solder dam (0.07mm clearance) around exposed vias. Use LPISM-SR8 solder mask for reduced wicking risk.”


We ensure precision via finishing with:

Laser-cleaned microvias (<0.15mm) → 99% void-free epoxy fill
Capillary-flow fillers: Prevent dimples on plugged surfaces

  • Auto-flag vias requiring plugging under BGAs/QFNs
    • Impedance modeling for tented vs. exposed RF vias
  • IST (Interconnect Stress Test): Validates plugged vias @ 150°C, 50 cycles
    • CAF Resistance: 85°C/85% RH testing per IPC-TM-650

TreatmentCost ImpactLead Time AddKey Benefit
TentingNoneNoneLowest cost
Plugging+15–25%2–3 daysPrevents wicking, improves CAF
Exposed+5%1 dayOptimal thermal dissipation
PCB Via Treatments Explained

Pro Tip: Use plugging only under BGAs and high-density areas to control costs.


  • Annular ring ≥ 0.05mm for mask adhesion
    • Avoid on vias within 0.1mm of SMT pads
  • Via aspect ratio ≤ 8:1 (e.g., 0.2mm via depth max for 0.025mm hole)
    • Specify fill material: Conductive epoxy (Ag-filled) or non-conductive
  • Add “SOLDER PASTE OPEN” in fab notes to prevent stencil coverage
    • Use ENIG finish for oxidation resistance

Choosing correct via treatments impacts manufacturing yield, field reliability, and electrical performance. Explicit specifications eliminate EQ delays and ensure optimal results.

[Your Company Name] delivers industry-leading via finishing:
<0.1mm microvia plugging for 01005 BGAs
Automated tenting validation via AOI
Exposed via solder dams to IPC Class 3 standards

Optimize your via strategy today!
→ [Download our Via Treatment Design Guide]
→ [Request a free DFM review]
→ [Get your custom IPC-4761 specification sheet]

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