Table of Contents
1、The Core Principle: Why 20H?
The 20H rule mandates that the power plane edge be recessed inward by a distance equivalent to 20 times the dielectric thickness (H) between the power and ground planes. This counteracts edge radiation effects—where varying electromagnetic fields at PCB edges emit interference, violating FCC/CE EMI limits by up to 15 dB. Empirical studies confirm:
– 20H indentation contains 70% of electromagnetic fields
– 100H indentation contains 98%
Electric field confinement through power plane indentation
2、When 20H Delivers Maximum Impact: Critical Conditions
Not all designs benefit equally. These four conditions amplify 20H’s effectiveness:
1. High-Speed Signal Edges
Rise/fall times <1 ns generate strong harmonics above 300 MHz—where radiation peaks.
2. Layering Architecture
Power planes must be sandwiched between two ground planes in an internal layer stackup, with ground planes extending 20H beyond the power zone.
3. Resonant Frequency Control
Power plane cavities must avoid resonant frequencies within the operating band (e.g., 1–6 GHz for 5G devices).
4. Minimum Layer Count
8+ layers optimize field containment. In 4-layer boards, effectiveness drops by 40%.
Table: 20H Rule Efficacy vs. Board Parameters
| Parameter | Optimal Value | Efficiency Loss if Violated |
| Rise/Fall Time | <1 ns | Up to 60% |
| Ground Plane Extension | ≥20H beyond power plane | 75% |
| PCB Layer Count | ≥8 layers | 30–40% |
| Resonant Frequency | Outside operating band | 50%+ |
3、Implementation Guide: From Theory to Manufacturing
Step 1: Calculate Indentation
– Measure dielectric thickness (H): Typical FR-4 H=0.2 mm → 20H=4 mm
– Design adjustment: For 100×80 mm power plane, reduce to 92×72 mm after 4mm indentation
Step 2: Stackup Configuration
Optimal 8-layer structure:
Step 3: Manufacturing Tolerances
– Etching compensation: Add 0.1 mm tolerance to indentation
– Layer alignment: X-ray registration ensures ±25μm layer-to-layer alignment
4、Material-Specific Considerations
FR-4 Boards
– Cost-efficient: 20H reduces EMI by 6–8 dB @ 2–4 GHz
– Limitation: Dielectric constant (Dk) variance ±15% above 5 GHz reduces predictability
High-Frequency Laminates (Rogers, Isola)
– Stable Dk: Enables precise 20H implementation up to 40 GHz
– Critical tweak: Reduce indentation to 15H for RF boards >20 GHz due to shorter wavelengths
5、Cost-Benefit Analysis: Is 20H Worth It?
| Cost Factor | Impact | ROI Scenario |
| PCB Area Loss | 5–8% usable area reduction | Acceptable for >6-layer boards |
| Tooling Complexity | +15% engineering time | Offset by 30% lower EMI test failures |
| EMI Compliance | $50k–$200k/test save | Critical for automotive (CISPR 25) |
6、Beyond 20H: Integrated EMC Strategy
Pair 20H with these techniques for maximum suppression:
1. Ground Via Stitching
Place grounding vias at 20H intervals along the power plane edge (λ/20 spacing at max frequency).
2. Edge Plating
Connect top/bottom ground planes with copper plating at board edges.
3. Absorptive Materials
Apply ferrite sheets (>500 MHz) or EMI coatings at critical radiation points.
7、Future-Proofing: 20H in Next-Gen Tech
– Flex-Rigid PCBs: Recess power planes in rigid sections only; flex zones use ground mesh.
– 3D ICs: Tiered power delivery networks require per-die 20H optimization.
– AI-Driven Simulation: ANSYS HFSS predicts ideal indentation (e.g., 18.7H) for 6G mmWave systems.
8、Conclusion: Best Practices for Implementation
1. Prioritize critical boards: Apply 20H to designs with >1 ns edge rates or >100 MHz clocks.
2. Verify stackup: Use impedance modeling tools (Polar SI9000) to confirm ground plane coverage.
3. Audit manufacturers: Ensure fab houses support controlled-depth etching (±0.05mm tolerance).
→ Download 20H Design Checklist: Includes layer stack templates, tolerance calculators, and EMI test protocols
