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The Impact of Through-Holes on Signal Transmission in Multi-layer PCBs


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In multi-layer PCBs, through-holes (vias) play a crucial role in signal transmission and electrical connections. Understanding the different types of vias and their impacts on PCB performance is essential for optimizing design and reducing costs.

Types of Vias in PCBs

1. Blind Vias

Connect the top or bottom surface to an inner layer without penetrating the entire board.

2. Buried Vias

Located entirely within the inner layers, not visible on the surface.

3. Through-Holes (Through Vias)

Extend through the entire board, facilitating interconnections across all layers.

Connecting holes

Impact on Cost and Manufacturing

Drilling costs constitute 30-40% of the total PCB manufacturing cost. Through-holes are preferred due to their ease of implementation and lower cost compared to blind and buried vias.

Parasitic Effects of Vias

1. Parasitic Capacitance

Via its own way on the existence of the parasitic capacitance, if the hole in the shop have been known to stratum segregation hole with a diameter of D2, through-hole pad with a diameter of the D1, PCB thickness of the plate for the T, substrate sheet for the dielectric constant ε, the hole is too similar to the size of parasitic capacitance: C = 1.41εTD1 / (D2-D1) Via parasitic capacitance of the circuit will cause the main impact is to extend the signal rise time, reducing the speed of the circuit. For example, to a thickness of the PCB board 50Mil, if used for the diameter of 10Mil, pad with a diameter of the hole 20Mil, copper pad on the floor and away from the area for 32Mil, we can calculate the approximate formula of the above had hole The parasitic capacitance is more or less: C = 1.41x4.4x0.050x0.020 / (0.032-0.020) = 0.517pF, this part of the increase in capacitance caused by changes in the amount of time: T10-90 = 2.2C (Z0 / 2) = 2.2 x0.517x (55 / 2) = 31.28ps. From these values can be seen, although a single through-hole caused by the parasitic capacitance of the slow increase in the effectiveness of the extension is not obvious, but if you take the line on many occasions in the hole used for switching between layers, the designer should consider carefully.

2. Parasitic Inductance

Similarly, the hole over the existence of the parasitic capacitance at the same time there is a parasitic inductance in high-speed digital circuit design, the hole over the parasitic inductance is often greater than the harmful effects of the parasitic capacitance. It's parasitic inductance in series will weaken the contribution to the bypass capacitor, weakening the entire power system, the effectiveness of the filter. We can use the following simple formula to calculate a through-hole similar to the parasitic inductance: L = 5.08h [ln (4h / d) +1] which means the L-off hole inductors, h is over the length of the hole, d is the center The drill diameter. From the style can be seen through-hole diameter of the impact of smaller inductors, and the greatest impact on the inductance is over the length of the hole. We will use the example above, you can calculate the inductance for the through-hole: L = 5.08x0.050 [ln (4x0.050/0.010) +1] = 1.015nH. If the signal rise time is 1ns, then the equivalent impedance of its size: XL = πL/T10-90 = 3.19Ω. Such resistance in the adoption of high-frequency current does not have been able to ignore, especially bearing in mind that bypass capacitor connected in the power level and time of the formation by the two through-hole, the hole had such a parasitic inductance will be doubled.

design of high-speed PCB

Design Considerations for High-Speed PCBs

1. Optimal Via Size

Balancing cost and signal integrity, typically 10/20Mil for 6-10 layer boards.

2. Minimize Layer Transitions

Reducing the number of vias to maintain signal integrity.

3. Shorten Power and Pin Distances

Minimizing inductance by keeping connections short and using larger vias for power.


Effective PCB design must account for the parasitic effects of through-holes to ensure high-speed signal transmission. By selecting appropriate via sizes and minimizing unnecessary vias, designers can enhance PCB performance and reduce manufacturing costs.

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