The USB 2.0 interface has a transmission rate of up to 480Mbps, and the maximum transmission bandwidth of USB 3.0 is up to 5Gbps, and USB 3.0 introduces full-duplex data transmission. The layout and routing of USB has its corresponding design requirements. The definition of USB 2.0 and USB 3.0 interface pins is shown in Figure 1.
Figure 1. USB 2.0 and USB 3.0 pin definition
1. PCB layout requirements of USB interface
1.1 The USB interface should be placed close to the edge of the board or structurally positioned, protruding out of the edge of the board to a certain position (except for direct plugging), for easy plugging and unplugging.
1.2 ESD and common mode inductance devices are close to the USB interface, and the order of placement is ESD-common mode inductance-resistance and capacitance.
1.3 Pay attention to the distance between ESD and USB, leave a certain distance, and consider the situation of post-welding.
1.4 When laying out, try to make the differential line the shortest to shorten the distance between the differential lines.
2. PCB wiring requirements of USB interface
2.1 USB should be differential, the impedance is controlled to 90Ω, and the ground is included. The total length should not exceed 1800mil.
2.2 Shorten the length of the traces as much as possible, and give priority to the wiring of high-speed USB differentials (RX, TX differentials). When routing USB differential traces, try to reduce layer-changing vias as much as possible, so that you can do better. To the control of impedance, avoid signal reflection.
2.3 The via holes will cause discontinuity in the line impedance. Add a pair of return ground via holes at the place where each hole is punched and changed layers for signal return flow and layer change.
2.4 If the positioning posts on both sides of the USB are connected to the protective ground, ensure that the distance from GND is 2MM when dividing, and drill more holes in the protective ground area to ensure sufficient connection, as shown in Figure 2.
5. Due to factors such as pin distribution, vias, and wiring space, the length of the differential line is easy to mismatch. Once the wiring length does not match, the timing will deviate, and it will also cause common-mode interference and reduce the signal quality. Therefore, corresponding compensation should be made for the mismatching of the differential pair to match the line length. The length difference is usually controlled within 5mil, and the compensation is carried out according to the differential equal length specification. The PCB layout requirements of USB 2.0 and 3.0 are compared, as shown in Table 1:
|Parameter||USB2.0 requirements||USB3.0 requirements|
|Trace impedance||Differential 90ohm±10%|
|Maximum delay difference within a differential pair||＜20mil||＜6mil|
|Trace length||＜6 inches|
|Number of vias allowed for each signal||Recommended not to exceed 4 and can not to exceed 6||Recommended not to exceed 2|
|Capacitance requirements||/||100nF ±20%, recommended to use 0201 package|
|Differential Pair Spacing||/||Recommended to be greater than or equal to 4 times the USB line width|
|USB and other signal issues||/||Recommended to be greater than or equal to 4 times the USB line width|
3. PCB design of Type C interface
USB Type C, also known as USB-C. It should be noted that Type C is just an interface and has nothing to do with the USB version. The highlight of this interface is the slimmer design, faster transmission speed (up to 10Gbps and more powerful power transmission (up to 100W). The biggest feature of the Type C double-sided pluggable interface is that it supports double-sided insertion of the USB interface, mainly for Thinner and slimmer devices. As shown in Figure 5, it is the pin definition of the Type C interface.
PCB design requirements for Type C interface:
1. ESD and common mode inductance devices are close to Type C interface, and the order of placement is ESD → common mode inductance → resistance capacitance; also pay attention to the distance between ESD and Type C, and leave a certain distance , considering the post-welding situation.
2. The coupling capacitor of the TX signal line should be placed close to the interface, and the coupling capacitor of the RX signal line is provided by the device, as shown in Figure 6.
3. The impedance of Type C differential traces is controlled at 90ohm±10%. In order to ensure the continuity of impedance, there should be a good reference plane and no cross-segmentation. The number of signal holes should not exceed 2.
4. Type C has four sets of RX/TX1-2 differential signals, two sets of D+/D- differential signals, and a total of six pairs of differential lines. The differential signal lines must be close to at least one ground plane, and it is best to be close to the ground plane on both sides. The line should be as short as possible, and the longest line should not exceed 6 inches.
5. Ensure that the length of the Type C differential line matches, the error of the equal length within the pair is <6mil, and the equal length follows the differential equal length specification.
6. To ensure the impact of Type C differential on inter-pairs or differential on other signals, it is recommended that the inter-pair spacing be greater than or equal to 4 times the Type C line width. Keep the spacing with other signals greater than or equal to 4 times the Type C line width as much as possible.
7. CC1/CC2 are two key pins with many functions: detecting connection, distinguishing the front and back, distinguishing DFP and UFP, that is, master-slave configuration Vbus, and the surface should be thickened when routing.
Note: When the working rate of the Type C connector is ≥8Gbps, please design according to the corresponding connector optimization suggestions.