With the large-scale increase in the complexity and integration of circuit system design, the challenges faced by electronic system design are no longer based on hardware tools, but on the operating frequency and signal integrity of transmission lines. Traditional circuit design knowledge can no longer be solved. Coping, this also begins to require electronic engineers to have knowledge of high-speed circuit design, because only by using high-speed circuits can the controllability of the design process be achieved. Today we will talk about what high-speed circuits are? How to determine the high-speed signal?
Generally speaking, if the frequency of a digital logic circuit has reached or exceeded 45MHz-50MHz, and the circuit operating above this frequency has occupied a certain component of the entire electronic system, it is called a high-speed circuit.
In fact, the harmonic frequency of the signal edge is higher than the frequency of the signal itself, and it is the rapidly changing rising and falling edges of the signal (or called: signal jump) that cause unexpected results of signal transmission. Therefore, it is generally agreed that if the line propagation delay is greater than 1/2 the rise time of the digital signal driver, such signals are considered to be high-speed signals and cause transmission line effects.
The propagation of the signal occurs at the moment when the signal state changes, such as rise or fall time. The signal takes a fixed amount of time from the driver to the receiver, and if the transit time is less than 1/2 the rise or fall time, then the reflected signal from the receiver will reach the driver before the signal changes state. Conversely, the reflected signal will reach the driver after the signal changes state. If the reflected signal is strong, the superimposed waveform may change the logic state.
Above we defined the preconditions for the occurrence of the transmission line effect, but how do we know whether the line delay is greater than 1/2 the signal rise time at the driving end? Generally, the typical value of the signal rise time can be given by the device manual, and the propagation of the signal The time is determined by the actual wiring length in PCB design.
The figure below shows the corresponding relationship between the signal rise time and the allowable wiring length delay.
The delay per unit inch on the PCB board is 0.167ns. However, if there are many via holes, there are many device pins, and there are many constraints set on the network line, the delay will increase. Generally, the signal rise time of high-speed logic devices is about 0.2ns. If there is a GaAs chip on the board, the maximum wiring length is 7.62mm.
Let Tr be the rise time of the signal, and Tpd be the propagation delay of the signal line. If Tr=4Tpd, the signal falls in the safe area. If 2Tpd=T=4Tpd, the signal falls in the uncertainty region. If T=2Tpd, the signal falls in the problem area. For signals that fall in areas of uncertainty and problem areas, high-speed routing methods should be used.