Boundary Scan testing

Boundary Scan testing was developed in the 1990s. With the advent of large-scale integrated circuits, the manufacturing process of printed circuit boards has evolved to small, micro, and thin. Traditional ICT testing has been unable to meet the testing requirements of such products.

Because the chip has many pins, the components are small, and the density of the board is particularly large, there is no way to test the probe. A new test technology has emerged. The Joint Test Action Group (JTAG) defines this new test method as boundary scan testing.

Advantages of boundary scan testing

1. Facilitate the fault location of the chip, quickly and accurately test whether the connection of the two chip pins is reliable, and improve the test efficiency.

2. The chip with JTAG interface has some pre-defined function modes built-in. The chip is placed in a specific function mode through the boundary scan channel to improve the flexibility of system control and facilitate system design.

At present, almost all complex IC chips have a JTAG control interface, and the JTAG control logic is simple, convenient, and easy to implement.

Principle

The boundary scan testing is implemented by attaching a boundary scan cell (BSC) and some additional test control logic to each I / O pin of the chip. The BSC is mainly composed of registers. Each I / O pin has a BSC, and each BSC has two data channels: one is a test data channel, test data input (TDI) and test data output (TDO), the other is normal data channel, normal data input (NDI) and normal data output (NDO).

In normal working state, input and output data can pass freely through each BSC, normal working data comes in from NDI and out from NDO. In the test state, you can select the channel through which data flows: for input IC (integrated circuit) pins, you can choose to input data from NDI or from TDI; for output IC pins, you can choose to output data from BSC to NDO You can also choose to output data from BSC to TDO.

In order to test the connection of two JTAG devices, first set the BSC of an output test pin of JTAG device 1 to high or low level and output to NDO. Then, let the input test pin of JTAG device 2 capture NDI value, and then output the captured data to TDO through the test data channel. By comparing the test results, you can quickly and accurately determine whether the two pins are connected reliably.

The IEEE 1149.1 standard specifies a four-wire serial interface (the fifth line is optional). This interface is called a test access port (TAP) and is used to access complex integrated circuit (IC) such as microprocessor, DSP, ASIC and CPLD. In addition to TAP, hybrid IC also includes shift registers and state machines to perform boundary-scan functions. The data entered into the chip on the TDI (test data input) leads is stored in the instruction register or a data register. Serial data leaves the chip from the TDO (test data output) lead. The boundary scan logic is clocked by a signal on the TCK (Test Clock), and the TMS (Test Mode Select) signal drives the state of the TAP controller. TRST (Test Reset) is optional.

Multiple ICs compatible with scan functions can be serially interconnected on the PCB to form one or more scan chains, each of which has its own TAP. Each scan chain provides electrical access from the serial TAP interface to every lead on every IC that is part of the chain. During normal operation, the IC performs its intended function as if the boundary scan circuit does not exist. However, when the device's scan logic is activated for testing or in-system programming, data can be transferred to the IC and read from the IC using a serial interface. This data can be used to activate the device core, send signals from the device leads to the PCB, read out the input leads of the PCB and read out the device output.